1. Field of the Invention
The present invention relates to a flash EEPROM cell and a method of manufacturing the same, and particularly, to a split gate type flash EEPROM cell and a method of manufacturing the same which not only can prevent an over-erasure of the flash EEPROM cell but also can decrease the cell area by forming a floating gate in the form of a spacer at the side wall of a select gate and by forming a control gate to surround the select gate and the floating gate.
2. Information Disclosure Statement
The flash EEPROM cell is a type of nonvolatile memory cell with the functions of electrical programming and erasing, the structure of which can mainly be classified as a stack structure or a split gate structure.
FIG. 1 shows a sectional view of a conventional flash EEPROM cell with a stack structure. FIG. 2 shows a sectional view of a conventional flash EEPROM cell with a split gate structure. A flash EEPROM cell with a stack structure or a split gate structure is basically composed of a p-type substrate 1, a tunnel oxide 2, a floating gate 3, an inter-poly oxide 4, a control gate 5, a drain region 6 and a source region 7. In particular, in the flash EEPROM cell with a split gate structure shown in FIG. 2, a select gate oxide 8 is additionally formed.
As shown in FIG. 1, the flash EEPROM cell with a stack structure has a small area such that the cell is over-erasure during the erasure operation of the cell. The split gate structure shown in FIG. 2 can solve the problem of such over-erasure. The split gate structure, however, has limitations in decreasing the cell area.